VINCENT BEROULLE

Keywords: Digital Design, VHDL, FPGA, Functional Verification, Safety, Security

Lectures on:

• Digital Architecture Design
• Functional Verification of Integrated Systems
• Introduction to Research

PAST PROJECTS

Coordinator of EMNESS ERASMUS+ Cooperation Partnership Project «European Master Network On Embedded System Security and Safety»

Academic Partners: University of Stuttgart, University of Freiburg, University of Piraeus, University of Barcelona (UPC), Politecnico di Torino, Grenoble INP Phelma

Vincent Beroulle is a Professor at Grenoble Institute of Technology and Head of the LCIS laboratory. He received an Engineering Degree from the National Polytechnic Institute of Grenoble (INPG) in 1996, and a Master’s Degree and a Ph.D. in Microelectronics from the University of Montpellier II in 1999 and 2002. His research focuses on the security and reliability of complex integrated circuits and systems, with particular emphasis on fault modeling and fault injection using emulation platforms.

https://cv.archives-ouvertes.fr/vincent-beroulle

CURRENT PROJECTS

CORAM – H4: Autonomous Vehicle Fleet Supervisory Platform

The CORAM-H4 project develops a supervisory platform for autonomous vehicle fleets. It integrates hardware security and fault-tolerance mechanisms to ensure system reliability. The project addresses hardware vulnerabilities, including fault injection attacks, and evaluates their impact on critical mobility functions.

Industrial Partners: BETI, GESTE, Orange

TWINSEC: Digital Twin for Native Security of Embedded Systems

TWINSEC aims to develop a digital twin of secure embedded systems. This virtual model enables the simulation and analysis of hardware behavior, physical attacks, and fault injection effects. It supports the design of secure-by-design systems at the micro-architectural level.

Academic Partners: CEA, TIMA, Verimag, EMSE, Inria, CentraleSupélec

POP (ANR): Power-Off Attacks on PUFs

The POP project investigates power-off attacks targeting Physical Unclonable Functions (PUFs). It analyzes how power disturbances and fault injection affect hardware security primitives. The project develops robust countermeasures to protect authentication and key generation mechanisms.

Coordinator: MSE
Academic Partners: TIMA, LHC, LCIS

ARSENE (PEPR Cyber): Secure Architectures for Embedded Digital Systems

ARSENE brings together the French research community on embedded systems security. The project develops secure hardware architectures, with a strong focus on RISC-V processors. It studies physical attacks, fault injection, and side-channel threats, and validates countermeasures through ASIC and FPGA demonstrators.

Coordinator: CEA
Academic Partners: Inria, IMT, TIMA, LabSTICC, LIRMM, Verimag, LCIS

ESSAIM‑CPS: Embedded Safe and Secure AI-based Methods for Interacting Cyber-Physical Systems

ESSAIM‑CPS develops AI-driven methods for safe and secure operation of interacting cyber-physical systems, with a focus on multi-robot coordination. The project addresses hardware security, fault injection, and robustness of embedded controllers, ensuring reliable behavior under disturbances and potential cyber-physical attacks.

Academic Partners / Coordinators: Grenoble INP – Esisar / LCIS (lead), ONERA

PAST PROJECTS

• EA Persyval CLAM project Coordinator “Cross Layer Fault Analysis for Microprocessor Architecture“ Academic Partner: LCIS (leader), TIMA, Verimag
• DETOXIO-S Project LCIS head (AURA Region funding), « Security evaluation of an FPGA-based application» Industrial Partners: Serenicity (leader), Clesse, Grenoble INP Esisar
• ANACONDA Project LCIS co-head (AURA Region funding), « Automated Cybersecurity Analysis with non-intrusive tools» Industrial Partners: Ponant Technologies (Leader), Rtone; Academic Partners: LCIS (leader), Grenoble Esisar
• Safe-RFID Project Coordinator (ANR JCJC funding): « Dependability and Security of RFID Systems », Dependability Improvement of RFID Systems, Vulnerability Analysis of RFID Systems, RFID Systems Model for Fault Simulation
• ANR LIESSE project « Laser-Induced fault Effects in Security-dedicated circuitS», Industrial Partner: ST Microelectronics; Academic Partners: LIRMM (Leader), LCIS, TIMA, ENSME, ONERA
• Safe-Air Project Coordinator (AURA Region funding): « Safety Evaluation of Aircraft Systems using Virtual Platforms» Industrial Partners: Thales Valence, AEDvices consulting; Academic Partners: LCIS (leader), TIMA, LHC

CURRENT PH.D. SUPERVISION

• Daniel THRION, "Vulnerability analysis of safe and secure systems", December 2023
• Mouad RABIAI, « Enhancing the Security of RISC-V Microarchitectures Against Laser Fault Injection : Fault Modeling and Countermeasure Development at the RTL Level », Novembre 2025
• Romain EGUINA, "Robutness of IA modules for critical applications", February 2026
• Issam LAHRECH, "Software-Configurable Hardware Countermeasure Against Physical Fault Attacks in a 32-bit RISC-V Core", October 2026

PREVIOUS PH.D. SUPERVISION

• Quentin JAYET, « Attestation d’un temps écoulé en embarqué », oral defense 9 December 2025
• Hiep Manh DO, « Design of Secure Tags using ECC », oral defense 6  October 2025
• Aghiles DAOUDI (TIMA/LCIS), “Design, Characterization and Security Evaluation of Physically Unclonable Functions », oral defense 23rd September 2025
• Ihab ALSHAER, “Cross-layer Fault Analysis on Microprocessor Architecture”, oral defense October 16th, 2023
• Amir ALI POUR, « Machine Learning for Modeling of PUF », oral defense December 2022
• Nikolaos Foivos POLYCHRONOUS, « Supervisor Design for Critical Embedded Systems », oral defense January 2023
• Zahra KAZEMI, “Fault Injection Attacks on Embedded Applications: Characterization and Evaluation”, oral defense February 2022
• Julie ROUX, « Evaluation de la robustesse de systèmes critiques par analyse cross-layer« , thèse soutenue le 7 janvier 2022
• Baptiste PESTOURIE, « UWB based Secure ranging and LOCalization« , thèse soutenue le 4 Décembre 2020, vidéo soutenance
• Johan LAURENT, « Modélisation de fautes utilisant la description RTL de microarchitectures pour l’analyse de vulnérabilité conjointe matérielle-logicielle« , thèse soutenue le 19 Novembre 2020, manuscrit, soutenance, vidéo soutenance
• Arash NEIJAT, « Détection de chevaux de Troie matériel combinée aux méthodes d’obfuscation » (2014-2019), soutenue le 25 Janvier 2019,
• Jérémy DUBEUF, « Etude et implémentation de contre-mesures matérielles pour la protection de dispositifs cryptographiques à base de courbes elliptiques » (2015-2018), CIFRE Maxim Integrated
• Athanasios PAPADIMITRIOU, « Modélisation au niveau RTL des attaques laser et Emulation pour l’évaluation de contre-mesures » (2012-2015), Projet ANR LIESSE
• Omar ABDELMALEK, « Conception et prototypage d’une architecture de tag UHF robuste » (2011-2015), Projet ANR SafeRFID
• Noémie BOHER, « Analyse, modélisation et conception de circuits analogiques de gestion de sécurité embarquée sur procédé CMOS« , (2012-2015), Thèse CIFRE STMicroelectronics
• Gilles FRITZ, « Méthode de monitoring pour la détection en ligne des défauts dans les systèmes RFID« , soutenue le 10 décembre 2012
• Youssef SERRESTOU, « Optimisation de la qualité de la vérification fonctionnelle par analyse de mutation« , soutenue le 8 décembre 2008
• Tu TRAN XUAN, thèse effectuée au CEA-LETI , « Méthode de test et conception en vue du test pour les réseaux sur puce asynchrones : application au réseau ANOC », soutenue le 12 février 2008.
• Yves JOANNON, CIFRE ST Microelectronics, « Qualification et génération automatique de stimuli pour le test de systèmes sur puces (SoC) analogiques mixtes et RF ». soutenue le 11 avril 2008.
• Rami KHOURI, »Modélisation comportementale en VHDL-AMS du lien RF pour la simulation et l’optimisation des systèmes RFID UHF et micro-ondes« ,soutenue le 28 mai 2007.