Thesis defense - Cross-Layer Fault Analysis for Microprocessor Architectures (CLAM)

Defense of Ihab ALSHAER for a Ph.D. thesis from the University of Grenoble-Alpes

Specialty: Nano Electronics and Nanotechnologies (NENT).

Thesis title: Cross-Layer Fault Analysis for Microprocessor Architectures (CLAM)

Doctoral school: Electronique, Electrotechnique, Automatique, Traitement du Signal (EEATS)

Location of the thesis defense: Auditorium A042, building AB Grenoble INP – Esisar, UGA 50 rue Barthélémy de Laffemas CS 10054 26902 Valence Cedex 09 – France

Zoom link: see below

Thesis directed by: Vincent Beroulle (LCIS)

Thesis co-supervised by: Paolo Maistri (TIMA), Brice Colombier (LabHC), Christophe Deleuze (LCIS)

Thesis prepared within the LCIS and TIMA labs.

Jury members:
M. Vincent BEROULLE Université Grenoble Alpes Thesis director
M. Jean-Max DUTERTRE Ecole Nationale Supérieure des Mines de Saint-Etienne Reporter
M. Pascal BENOIT Université Montpellier 2 Reporter
M. Giorgio DI NATALE CNRS Examiner
Mme Marie-laure POTET Université Grenoble Alpes Examiner
M. Athanasios PAPADIMITRIOU University of the Peloponnese Examiner
M. Christophe DELEUZE Université Grenoble Alpes Guest

Keywords:
Hardware security, Fault injection attacks, Fault modeling, RTL fault simulation, Variable-length instruction set, Vulnerability analysis.

ABSTRACT:
With the widespread use of embedded system devices, hardware designers and software developers started paying more attention to security issues in order to protect these devices from potential threats.
Among these threats, physical attacks pose a significant risk, with fault injection attacks being a very powerful attack method. Nevertheless, an inaccurate understanding of the impact caused by fault injection can result in the proposal of either excessive or insufficient protections for these devices. This, in turn, adversely affects the performance/cost ratio and/or the overall device security.
To address this challenge, realistic fault models are indispensable for comprehending the effects of fault injection. Such models play a crucial role in analyzing potential vulnerabilities in software codes and hardware designs, thereby enabling the protection of digital systems against such attacks while maintaining cost-effectiveness. However, relying solely on limited observations of faulty microprocessors poses challenges when inferring fault models, ultimately limiting our understanding of the effects caused by these faults.
This thesis presents experimental evidence that highlights the challenges in characterizing and modeling the effects of fault injection when considering a single layer of system levels.
Therefore, a cross-layer analysis approach is introduced to bridge the gap between previous studies and enable a better understanding of the effects of the faults.
Furthermore, the thesis demonstrates the successful implementation of this methodology, resulting in the inference of reliable and novel fault models at both software and hardware levels of abstraction.
Moreover, the applicability of these fault models is showcased across various target programs, target devices, and different fault injection techniques.
Finally, the thesis illustrates how these fault models can be leveraged to perform vulnerability analysis of software codes, offering the capability to develop suitable and cost-effective countermeasures.

Zoom meeting

https://grenoble-inp.zoom.us/j/99068963445
Secret code: 744690